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| author | Miodrag Dinic <miodrag.dinic@imgtec.com> | 2015-06-11 16:21:18 +0200 |
|---|---|---|
| committer | Miodrag Dinic <miodrag.dinic@imgtec.com> | 2015-06-16 12:08:43 +0200 |
| commit | 5e29087a9444d323bbab1ed7c7120ea7ef3739f2 (patch) | |
| tree | 32d8a485a824551215176a39af4ec8fbecb9e421 | |
| parent | 5f25a532cb29ca9090343b1fda8815f46be9b213 (diff) | |
| download | qemu-android-5e29087a9444d323bbab1ed7c7120ea7ef3739f2.tar.gz | |
target-mips: fix updating BadVAddr for misaligned accesses
Update BadVAddr correctly for the case of misaligned block accesses.
The address reported by BadVAddr on page permission or TLB miss exceptions
must be a byte address in the misaligned access for a page on which the
exception is reported, but may be any such byte address.
It is not required to be the lowest.
Cherry-picked from PRPL QEMU :
https://github.com/yongbok/prpl-qemu/commit/3e5e2b5f6affab2c367e8e774105877bc0f505f3
3e5e2b5f target-mips: fix updating BadVAddr for misaligned accesses
Change-Id: I489effe5b4c0c693dca7a41a01157c3477cea47c
| -rw-r--r-- | target-mips/helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 48181f2296..bfcffa2b60 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -632,6 +632,9 @@ bool cpu_mips_validate_access(CPUMIPSState *env, target_ulong address, ret = get_physical_address(env, &physical, &prot, addr, rw, access_type); if (ret != TLBRET_MATCH) { + if (ret != TLBRET_BADADDR && addr > badvaddr) { + badvaddr = addr; + } raise_mmu_exception(env, badvaddr, rw, ret); return false; } |