Revert "minigbm: Add support for CCS Media Compression on MTL"

Revert reason: Seeing regression with media compression patches.
Video playback is falling back to SW decode.
Reverting media compression for now.

This reverts commit 4492f456512b0c74ef27e8ad46db754025920bee.

Change-Id: I20b84a90f7e7b49559db6fe04e976db159ddfb17
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/minigbm/+/5343756
Reviewed-by: Hirokazu Honda <hiroh@chromium.org>
Commit-Queue: Hirokazu Honda <hiroh@chromium.org>

2 files changed, 25 insertions, 67 deletions

diff --git a/drv.h b/drv.h
index bf00c9f..3dedfd1 100644
--- a/drv.h
+++ b/drv.h
@@ -98,22 +98,6 @@ extern "C" {
 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
 #endif
 
-#ifndef I915_FORMAT_MOD_4_TILED_MTL_MC_CCS
-//TODO: remove this defination once drm_fourcc.h contains it.
-/*
- * Intel color control surfaces (CCS) for display ver 14 media compression
- *
- * The main surface is tile4 and at plane index 0, the CCS is linear and
- * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
- * main surface. In other words, 4 bits in CCS map to a main surface cache
- * line pair. The main surface pitch is required to be a multiple of four
- * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
- * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
- * planes 2 and 3 for the respective CCS.
- */
-#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
-#endif
-
 // clang-format on
 struct driver;
 struct bo;
diff --git a/i915.c b/i915.c
index 3f6972e..b9e377f 100644
--- a/i915.c
+++ b/i915.c
@@ -46,9 +46,7 @@ static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_F
 						 DRM_FORMAT_MOD_LINEAR };
 
 static const uint64_t xe_lpdp_modifier_order[] = { I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
-						   I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
-						   I915_FORMAT_MOD_4_TILED,
-						   I915_FORMAT_MOD_X_TILED,
+						   I915_FORMAT_MOD_4_TILED, I915_FORMAT_MOD_X_TILED,
 						   DRM_FORMAT_MOD_LINEAR };
 
 struct modifier_support_t {
@@ -303,14 +301,6 @@ static int i915_add_combinations(struct driver *drv)
 		drv_add_combinations(drv, scanout_render_formats,
 				     ARRAY_SIZE(scanout_render_formats), &metadata_4_tiled,
 				     scanout_and_render_not_linear);
-
-		metadata_4_tiled.priority = 4;
-		metadata_4_tiled.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
-		drv_add_combination(drv, DRM_FORMAT_NV12, &metadata_4_tiled,
-				    unset_flags(nv12_usage, BO_USE_PROTECTED));
-		drv_add_combination(drv, DRM_FORMAT_P010, &metadata_4_tiled,
-				    unset_flags(p010_usage, BO_USE_PROTECTED));
-
 	} else {
 		struct format_metadata metadata_y_tiled = { .tiling = I915_TILING_Y,
 							    .priority = 3,
@@ -572,8 +562,7 @@ static size_t i915_num_planes_from_modifier(struct driver *drv, uint32_t format,
 	    modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS) {
 		assert(num_planes == 1);
 		return 2;
-	} else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
-		   modifier == I915_FORMAT_MOD_4_TILED_MTL_MC_CCS) {
+	} else if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) {
 		assert(num_planes == 2);
 		return 4;
 	}
@@ -605,6 +594,11 @@ static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t heig
 		/* TODO(b/323863689): Account for driver's bandwidth compression in minigbm for
 		 * media compressed buffers. */
 	}
+	if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS &&
+	    !(format == DRM_FORMAT_NV12 || format == DRM_FORMAT_P010)) {
+		drv_loge("Media compression is only supported for NV12 and P010\n");
+		return -EINVAL;
+	}
 
 	/*
 	 * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
@@ -662,7 +656,6 @@ static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t heig
 		break;
 	case I915_FORMAT_MOD_4_TILED:
 	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
-	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 		bo->meta.tiling = I915_TILING_4;
 		break;
 	}
@@ -789,16 +782,8 @@ static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t heig
 		/* Total number of planes & sizes */
 		bo->meta.num_planes = plane + a_plane;
 		bo->meta.total_size = offset;
-	} else if (modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS ||
-		   modifier == I915_FORMAT_MOD_4_TILED_MTL_MC_CCS) {
-		assert(!(bo->meta.use_flags & BO_USE_PROTECTED));
-		assert(modifier != I915_FORMAT_MOD_4_TILED_MTL_MC_CCS ||
-			(format == DRM_FORMAT_NV12 || format == DRM_FORMAT_P010));
-		assert(drv_num_planes_from_format(format) > 0);
+	} else if (modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS) {
 
-		uint32_t offset = 0, stride = 0;
-		size_t plane = 0;
-		size_t a_plane = 0;
 		/*
 		 * considering only 128 byte compression and one cache line of
 		 * aux buffer(64B) contains compression status of 4-Y tiles.
@@ -806,40 +791,30 @@ static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t heig
 		 * line stride(bytes) is 4 * 128B
 		 * and tile stride(lines) is 32L
 		 */
-		for(plane = 0; plane < drv_num_planes_from_format(format); plane++) {
-			stride = ALIGN(drv_stride_from_format(format, width, plane), 512);
-
-			height = ALIGN(drv_height_from_format(format, height, plane), 32);
+		uint32_t stride = ALIGN(drv_stride_from_format(format, width, 0), 512);
+		stride = ALIGN(stride, 256);
 
-			bo->meta.strides[plane] = stride;
-			/* size calculation and alignment are 64KB aligned for the generic case
-			 * size as per spec
-			 */
-			bo->meta.sizes[plane] = ALIGN(stride * height, 512 * 128);
+		height = ALIGN(drv_height_from_format(format, height, 0), 32);
 
-			/* and a special case of 1MB aligment on MTL */
-			if (plane == 1 && (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_P010))
-			  offset = ALIGN(offset, 1024 * 1024);
 
-			bo->meta.offsets[plane] = offset;
-			offset += bo->meta.sizes[plane];
-		}
+		bo->meta.strides[0] = stride;
+		/* size calculation and alignment are 64KB aligned
+		 * size as per spec
+		 */
+		bo->meta.sizes[0] = ALIGN(stride * height, 65536);
+		bo->meta.offsets[0] = 0;
 
 		/* Aux buffer is linear and page aligned. It is placed after
 		 * other planes and aligned to main buffer stride.
 		 */
-		for(a_plane = 0; a_plane < plane; a_plane++) {
-			stride = bo->meta.strides[a_plane] / 8;
-			bo->meta.strides[a_plane + plane] = stride;
+		bo->meta.strides[1] = bo->meta.strides[0] / 8;
 
-			/* Aligned to page size */
-			bo->meta.sizes[a_plane + plane] = ALIGN(bo->meta.sizes[a_plane] / 256, getpagesize());
-			bo->meta.offsets[a_plane + plane] = offset;
-			/* next buffer offset */
-			offset += bo->meta.sizes[plane + a_plane];
-		}
-		bo->meta.num_planes = a_plane + plane;
-		bo->meta.total_size = offset;
+		/* Aligned to page size */
+		bo->meta.sizes[1] = ALIGN(bo->meta.sizes[0] / 256, getpagesize());
+		bo->meta.offsets[1] = bo->meta.sizes[0];
+		/* Total number of planes & sizes */
+		bo->meta.num_planes = 2;
+		bo->meta.total_size = bo->meta.sizes[0] + bo->meta.sizes[1];
 	} else {
 		return i915_bo_from_format(bo, width, height, format);
 	}
@@ -958,8 +933,7 @@ static void *i915_bo_map(struct bo *bo, struct vma *vma, uint32_t map_flags)
 	    (bo->meta.format_modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS) ||
 	    (bo->meta.format_modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) ||
 	    (bo->meta.format_modifier == I915_FORMAT_MOD_4_TILED) ||
-	    (bo->meta.format_modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS) ||
-	    (bo->meta.format_modifier == I915_FORMAT_MOD_4_TILED_MTL_MC_CCS))
+	    (bo->meta.format_modifier == I915_FORMAT_MOD_4_TILED_MTL_RC_CCS))
 		return MAP_FAILED;
 
 	if (bo->meta.tiling == I915_TILING_NONE) {