diff options
Diffstat (limited to 'ext/ipp/include/ippcpdefs.h')
| -rw-r--r-- | ext/ipp/include/ippcpdefs.h | 123 |
1 files changed, 76 insertions, 47 deletions
diff --git a/ext/ipp/include/ippcpdefs.h b/ext/ipp/include/ippcpdefs.h index 083c360..974b54a 100644 --- a/ext/ipp/include/ippcpdefs.h +++ b/ext/ipp/include/ippcpdefs.h @@ -1,31 +1,49 @@ -/*############################################################################ - # Copyright 1999-2018 Intel Corporation - # - # Licensed under the Apache License, Version 2.0 (the "License"); - # you may not use this file except in compliance with the License. - # You may obtain a copy of the License at - # - # http://www.apache.org/licenses/LICENSE-2.0 - # - # Unless required by applicable law or agreed to in writing, software - # distributed under the License is distributed on an "AS IS" BASIS, - # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - # See the License for the specific language governing permissions and - # limitations under the License. - ############################################################################*/ - -/* -// Intel(R) Integrated Performance Primitives (Intel(R) IPP) -// Cryptographic Primitives (ippCP) definitions. -// -// -*/ +/******************************************************************************* +* Copyright 2012-2018 Intel Corporation +* All Rights Reserved. +* +* If this software was obtained under the Intel Simplified Software License, +* the following terms apply: +* +* The source code, information and material ("Material") contained herein is +* owned by Intel Corporation or its suppliers or licensors, and title to such +* Material remains with Intel Corporation or its suppliers or licensors. The +* Material contains proprietary information of Intel or its suppliers and +* licensors. The Material is protected by worldwide copyright laws and treaty +* provisions. No part of the Material may be used, copied, reproduced, +* modified, published, uploaded, posted, transmitted, distributed or disclosed +* in any way without Intel's prior express written permission. No license under +* any patent, copyright or other intellectual property rights in the Material +* is granted to or conferred upon you, either expressly, by implication, +* inducement, estoppel or otherwise. Any license under such intellectual +* property rights must be express and approved by Intel in writing. +* +* Unless otherwise agreed by Intel in writing, you may not remove or alter this +* notice or any other notice embedded in Materials by Intel or Intel's +* suppliers or licensors in any way. +* +* +* If this software was obtained under the Apache License, Version 2.0 (the +* "License"), the following terms apply: +* +* You may not use this file except in compliance with the License. You may +* obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +* +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ -/* +/* // Intel(R) Integrated Performance Primitives (Intel(R) IPP) +// Cryptographic Primitives (ippCP) definitions // Basic Types and Macro Definitions -// -// +// +// */ @@ -124,6 +142,8 @@ extern "C" { #define IPP_UINT64 unsigned long long #endif +#define IPP_COUNT_OF( obj ) (sizeof(obj)/sizeof(obj[0])) + #define IPP_PI ( 3.14159265358979323846 ) /* ANSI C does not support M_PI */ #define IPP_2PI ( 6.28318530717958647692 ) /* 2*pi */ #define IPP_PI2 ( 1.57079632679489661923 ) /* pi/2 */ @@ -272,26 +292,26 @@ typedef enum { #ifndef IPP_CPU_FEATURES__ #define IPP_CPU_FEATURES__ -#define ippCPUID_MMX 0x00000001 /* Intel(R) Architecture MMX technology supported */ -#define ippCPUID_SSE 0x00000002 /* Intel(R) Streaming SIMD Extensions */ -#define ippCPUID_SSE2 0x00000004 /* Intel(R) Streaming SIMD Extensions 2 */ -#define ippCPUID_SSE3 0x00000008 /* Intel(R) Streaming SIMD Extensions 3 */ -#define ippCPUID_SSSE3 0x00000010 /* Supplemental Streaming SIMD Extensions 3 */ -#define ippCPUID_MOVBE 0x00000020 /* Intel(R) MOVBE instruction */ -#define ippCPUID_SSE41 0x00000040 /* Intel(R) Streaming SIMD Extensions 4.1 */ -#define ippCPUID_SSE42 0x00000080 /* Intel(R) Streaming SIMD Extensions 4.2 */ +#define ippCPUID_MMX 0x00000001 /* Intel(R) architecture with MMX(TM) technology supported */ +#define ippCPUID_SSE 0x00000002 /* Intel(R) Streaming SIMD Extensions instruction set */ +#define ippCPUID_SSE2 0x00000004 /* Intel(R) Streaming SIMD Extensions 2 instruction set */ +#define ippCPUID_SSE3 0x00000008 /* Intel(R) Streaming SIMD Extensions 3 instruction set */ +#define ippCPUID_SSSE3 0x00000010 /* Supplemental Streaming SIMD Extensions 3 instruction set */ +#define ippCPUID_MOVBE 0x00000020 /* Intel(R) instruction MOVBE */ +#define ippCPUID_SSE41 0x00000040 /* Intel(R) Streaming SIMD Extensions 4.1 instruction set */ +#define ippCPUID_SSE42 0x00000080 /* Intel(R) Streaming SIMD Extensions 4.2 instruction set */ #define ippCPUID_AVX 0x00000100 /* Intel(R) Advanced Vector Extensions instruction set */ #define ippAVX_ENABLEDBYOS 0x00000200 /* Intel(R) Advanced Vector Extensions instruction set is supported by OS */ #define ippCPUID_AES 0x00000400 /* Intel(R) AES New Instructions */ -#define ippCPUID_CLMUL 0x00000800 /* Intel(R) CLMUL instruction */ +#define ippCPUID_CLMUL 0x00000800 /* Intel(R) instruction PCLMULQDQ */ #define ippCPUID_ABR 0x00001000 /* Reserved */ -#define ippCPUID_RDRAND 0x00002000 /* Intel(R) RDRAND instruction */ -#define ippCPUID_F16C 0x00004000 /* Intel(R) F16C new instructions */ -#define ippCPUID_AVX2 0x00008000 /* Intel(R) Advanced Vector Extensions 2 instruction set */ -#define ippCPUID_ADCOX 0x00010000 /* Intel(R) ADOX/ADCX new instructions */ -#define ippCPUID_RDSEED 0x00020000 /* Intel(R) RDSEED instruction */ -#define ippCPUID_PREFETCHW 0x00040000 /* Intel(R) PREFETCHW instruction */ -#define ippCPUID_SHA 0x00080000 /* Intel(R) SHA new instructions */ +#define ippCPUID_RDRAND 0x00002000 /* Intel(R) instruction RDRAND */ +#define ippCPUID_F16C 0x00004000 /* Intel(R) instruction F16C */ +#define ippCPUID_AVX2 0x00008000 /* Intel(R) Advanced Vector Extensions 2 */ +#define ippCPUID_ADCOX 0x00010000 /* Intel(R) instructions ADOX/ADCX */ +#define ippCPUID_RDSEED 0x00020000 /* Intel(R) instruction RDSEED */ +#define ippCPUID_PREFETCHW 0x00040000 /* Intel(R) instruction PREFETCHW */ +#define ippCPUID_SHA 0x00080000 /* Intel(R) Secure Hash Algorithm Extensions */ #define ippCPUID_AVX512F 0x00100000 /* Intel(R) Advanced Vector Extensions 512 Foundation instruction set */ #define ippCPUID_AVX512CD 0x00200000 /* Intel(R) Advanced Vector Extensions 512 CD instruction set */ #define ippCPUID_AVX512ER 0x00400000 /* Intel(R) Advanced Vector Extensions 512 ER instruction set */ @@ -327,6 +347,8 @@ extern "C" { typedef signed int IppStatus; /* start of common with ippCrypto part - any changes MUST be done in both repositories - IPP & ippCrypto */ +#define ippStsCpuNotSupportedErr -9999 /* The target CPU is not supported. */ +#define ippStsUnknownStatusCodeErr -216 /* Unknown status code. */ #define ippStsLoadDynErr -221 /* Error when loading the dynamic library. */ #define ippStsLengthErr -15 /* Incorrect value for string length. */ #define ippStsNotSupportedModeErr -14 /* The requested mode is currently not supported. */ @@ -347,6 +369,7 @@ typedef signed int IppStatus; #define ippStsNoOperation 1 /* No operation has been executed. */ #define ippStsDivByZero 2 /* Zero value(s) for the divisor in the Div function. */ #define ippStsWaterfall 43 /* Cannot load required library, waterfall is used. */ +#define ippStsFeaturesCombination 51 /* Wrong combination of features. */ /* end of common with ippCrypto part */ #ifdef __cplusplus @@ -373,9 +396,10 @@ typedef signed int IppStatus; #define ippStsPaddingSchemeErr -1002 /* Invalid padding scheme. */ #define ippStsBadModulusErr -1001 /* Bad modulus caused a failure in module inversion. */ #define ippStsInsufficientEntropy 25 /* Generation of the prime/key failed due to insufficient entropy in the random seed and stimulus bit string. */ +#define ippStsNotSupportedCpu 36 /* The CPU is not supported. */ /* end of ippCrypto specific statuses - any changes MUST be done in both repositories - IPP & ippCrypto */ -#ifndef IPPCPDEFS_H__ +#if (!defined IPPCPDEFS_H__) || defined( _OWN_BLDPCS ) #define IPPCPDEFS_H__ #ifdef __cplusplus @@ -528,6 +552,7 @@ typedef struct _cpAES_CMAC IppsAES_CMACState; */ #define BN_MAXBITSIZE (16*1024) /* bn max size (bits) */ + typedef enum { ippBigNumNEG = 0, IppsBigNumNEG = 0, ippBigNumPOS = 1, IppsBigNumPOS = 1 @@ -575,7 +600,7 @@ typedef IppStatus (IPP_STDCALL *IppBitSupplier)(Ipp32u* pRand, int nBits, void* // ========================================================= */ #define MIN_RSA_SIZE (8) -#define MAX_RSA_SIZE (8*1024) +#define MAX_RSA_SIZE (16*1024) typedef struct _cpRSA IppsRSAState; @@ -758,20 +783,24 @@ typedef struct { int elementLen; } IppsGFpInfo; -#endif /* _OWN_BLDPCS */ +typedef struct _cpStateECES_SM2 IppsECESState_SM2; + +#endif /* !defined( _OWN_BLDPCS ) */ + #ifndef _PCS -IPPAPI( IppStatus, ippcpSetNumThreads, ( int numThr )) -IPPAPI( IppStatus, ippcpGetNumThreads, (int* pNumThr) ) IPPAPI( IppStatus, ippcpGetCpuFeatures, ( Ipp64u* pFeaturesMask )) IPPAPI( IppStatus, ippcpSetCpuFeatures, ( Ipp64u features )) IPPAPI( Ipp64u, ippcpGetEnabledCpuFeatures, ( void ) ) +IPPAPI( IppStatus, ippcpSetNumThreads, ( int numThr )) IPPAPI( IppStatus, ippcpInit,( void )) +IPPAPI( IppStatus, ippcpGetNumThreads, (int* pNumThr) ) IPPAPI( const char*, ippcpGetStatusString, ( IppStatus StsCode )) IPPAPI( int, ippcpGetEnabledNumThreads, ( void ) ) +IPPAPI( Ipp64u, ippcpGetCpuClocks, (void) ) #endif #ifdef __cplusplus } #endif -#endif /* IPPCPDEFS_H__ */ +#endif /* !defined IPPCPDEFS_H__ || defined( _OWN_BLDPCS ) */ |