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Diffstat (limited to 'share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/DEC-Alpha-Options.html')
| -rw-r--r-- | share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/DEC-Alpha-Options.html | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/DEC-Alpha-Options.html b/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/DEC-Alpha-Options.html index 53aea66..e52f569 100644 --- a/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/DEC-Alpha-Options.html +++ b/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/DEC-Alpha-Options.html @@ -59,7 +59,7 @@ Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel-Options" <p>These ‘<samp><span class="samp">-m</span></samp>’ options are defined for the DEC Alpha implementations: <dl> -<dt><code>-mno-soft-float</code><dt><code>-msoft-float</code><dd><a name="index-mno_002dsoft_002dfloat-1282"></a><a name="index-msoft_002dfloat-1283"></a>Use (do not use) the hardware floating-point instructions for +<dt><code>-mno-soft-float</code><dt><code>-msoft-float</code><dd><a name="index-mno_002dsoft_002dfloat-1284"></a><a name="index-msoft_002dfloat-1285"></a>Use (do not use) the hardware floating-point instructions for floating-point operations. When <samp><span class="option">-msoft-float</span></samp> is specified, functions in <samp><span class="file">libgcc.a</span></samp> will be used to perform floating-point operations. Unless they are replaced by routines that emulate the @@ -72,7 +72,7 @@ them. <p>Note that Alpha implementations without floating-point operations are required to have floating-point registers. - <br><dt><code>-mfp-reg</code><dt><code>-mno-fp-regs</code><dd><a name="index-mfp_002dreg-1284"></a><a name="index-mno_002dfp_002dregs-1285"></a>Generate code that uses (does not use) the floating-point register set. + <br><dt><code>-mfp-reg</code><dt><code>-mno-fp-regs</code><dd><a name="index-mfp_002dreg-1286"></a><a name="index-mno_002dfp_002dregs-1287"></a>Generate code that uses (does not use) the floating-point register set. <samp><span class="option">-mno-fp-regs</span></samp> implies <samp><span class="option">-msoft-float</span></samp>. If the floating-point register set is not used, floating-point operands are passed in integer registers as if they were integers and floating-point results are passed @@ -84,7 +84,7 @@ option. <p>A typical use of this option is building a kernel that does not use, and hence need not save and restore, any floating-point registers. - <br><dt><code>-mieee</code><dd><a name="index-mieee-1286"></a>The Alpha architecture implements floating-point hardware optimized for + <br><dt><code>-mieee</code><dd><a name="index-mieee-1288"></a>The Alpha architecture implements floating-point hardware optimized for maximum performance. It is mostly compliant with the IEEE floating-point standard. However, for full compliance, software assistance is required. This option generates code fully IEEE-compliant code @@ -95,7 +95,7 @@ able to correctly support denormalized numbers and exceptional IEEE values such as not-a-number and plus/minus infinity. Other Alpha compilers call this option <samp><span class="option">-ieee_with_no_inexact</span></samp>. - <br><dt><code>-mieee-with-inexact</code><dd><a name="index-mieee_002dwith_002dinexact-1287"></a>This is like <samp><span class="option">-mieee</span></samp> except the generated code also maintains + <br><dt><code>-mieee-with-inexact</code><dd><a name="index-mieee_002dwith_002dinexact-1289"></a>This is like <samp><span class="option">-mieee</span></samp> except the generated code also maintains the IEEE <var>inexact-flag</var>. Turning on this option causes the generated code to implement fully-compliant IEEE math. In addition to <code>_IEEE_FP</code>, <code>_IEEE_FP_EXACT</code> is defined as a preprocessor @@ -105,7 +105,7 @@ very little code that depends on the <var>inexact-flag</var>, you should normally not specify this option. Other Alpha compilers call this option <samp><span class="option">-ieee_with_inexact</span></samp>. - <br><dt><code>-mfp-trap-mode=</code><var>trap-mode</var><dd><a name="index-mfp_002dtrap_002dmode-1288"></a>This option controls what floating-point related traps are enabled. + <br><dt><code>-mfp-trap-mode=</code><var>trap-mode</var><dd><a name="index-mfp_002dtrap_002dmode-1290"></a>This option controls what floating-point related traps are enabled. Other Alpha compilers call this option <samp><span class="option">-fptm </span><var>trap-mode</var></samp>. The trap mode can be set to one of four values: @@ -123,7 +123,7 @@ completion (see Alpha architecture manual for details). <br><dt>‘<samp><span class="samp">sui</span></samp>’<dd>Like ‘<samp><span class="samp">su</span></samp>’, but inexact traps are enabled as well. </dl> - <br><dt><code>-mfp-rounding-mode=</code><var>rounding-mode</var><dd><a name="index-mfp_002drounding_002dmode-1289"></a>Selects the IEEE rounding mode. Other Alpha compilers call this option + <br><dt><code>-mfp-rounding-mode=</code><var>rounding-mode</var><dd><a name="index-mfp_002drounding_002dmode-1291"></a>Selects the IEEE rounding mode. Other Alpha compilers call this option <samp><span class="option">-fprm </span><var>rounding-mode</var></samp>. The <var>rounding-mode</var> can be one of: @@ -143,7 +143,7 @@ rounding towards plus infinity. Thus, unless your program modifies the <var>fpcr</var>, ‘<samp><span class="samp">d</span></samp>’ corresponds to round towards plus infinity. </dl> - <br><dt><code>-mtrap-precision=</code><var>trap-precision</var><dd><a name="index-mtrap_002dprecision-1290"></a>In the Alpha architecture, floating-point traps are imprecise. This + <br><dt><code>-mtrap-precision=</code><var>trap-precision</var><dd><a name="index-mtrap_002dprecision-1292"></a>In the Alpha architecture, floating-point traps are imprecise. This means without software assistance it is impossible to recover from a floating trap and program execution normally needs to be terminated. GCC can generate code that can assist operating system trap handlers @@ -165,14 +165,14 @@ instruction that caused a floating-point exception. <p>Other Alpha compilers provide the equivalent options called <samp><span class="option">-scope_safe</span></samp> and <samp><span class="option">-resumption_safe</span></samp>. - <br><dt><code>-mieee-conformant</code><dd><a name="index-mieee_002dconformant-1291"></a>This option marks the generated code as IEEE conformant. You must not + <br><dt><code>-mieee-conformant</code><dd><a name="index-mieee_002dconformant-1293"></a>This option marks the generated code as IEEE conformant. You must not use this option unless you also specify <samp><span class="option">-mtrap-precision=i</span></samp> and either <samp><span class="option">-mfp-trap-mode=su</span></samp> or <samp><span class="option">-mfp-trap-mode=sui</span></samp>. Its only effect is to emit the line ‘<samp><span class="samp">.eflag 48</span></samp>’ in the function prologue of the generated assembly file. Under DEC Unix, this has the effect that IEEE-conformant math library routines will be linked in. - <br><dt><code>-mbuild-constants</code><dd><a name="index-mbuild_002dconstants-1292"></a>Normally GCC examines a 32- or 64-bit integer constant to + <br><dt><code>-mbuild-constants</code><dd><a name="index-mbuild_002dconstants-1294"></a>Normally GCC examines a 32- or 64-bit integer constant to see if it can construct it from smaller constants in two or three instructions. If it cannot, it will output the constant as a literal and generate code to load it from the data segment at run time. @@ -184,18 +184,18 @@ using code, even if it takes more instructions (the maximum is six). loader. Itself a shared library, it must relocate itself in memory before it can find the variables and constants in its own data segment. - <br><dt><code>-malpha-as</code><dt><code>-mgas</code><dd><a name="index-malpha_002das-1293"></a><a name="index-mgas-1294"></a>Select whether to generate code to be assembled by the vendor-supplied + <br><dt><code>-malpha-as</code><dt><code>-mgas</code><dd><a name="index-malpha_002das-1295"></a><a name="index-mgas-1296"></a>Select whether to generate code to be assembled by the vendor-supplied assembler (<samp><span class="option">-malpha-as</span></samp>) or by the GNU assembler <samp><span class="option">-mgas</span></samp>. - <br><dt><code>-mbwx</code><dt><code>-mno-bwx</code><dt><code>-mcix</code><dt><code>-mno-cix</code><dt><code>-mfix</code><dt><code>-mno-fix</code><dt><code>-mmax</code><dt><code>-mno-max</code><dd><a name="index-mbwx-1295"></a><a name="index-mno_002dbwx-1296"></a><a name="index-mcix-1297"></a><a name="index-mno_002dcix-1298"></a><a name="index-mfix-1299"></a><a name="index-mno_002dfix-1300"></a><a name="index-mmax-1301"></a><a name="index-mno_002dmax-1302"></a>Indicate whether GCC should generate code to use the optional BWX, + <br><dt><code>-mbwx</code><dt><code>-mno-bwx</code><dt><code>-mcix</code><dt><code>-mno-cix</code><dt><code>-mfix</code><dt><code>-mno-fix</code><dt><code>-mmax</code><dt><code>-mno-max</code><dd><a name="index-mbwx-1297"></a><a name="index-mno_002dbwx-1298"></a><a name="index-mcix-1299"></a><a name="index-mno_002dcix-1300"></a><a name="index-mfix-1301"></a><a name="index-mno_002dfix-1302"></a><a name="index-mmax-1303"></a><a name="index-mno_002dmax-1304"></a>Indicate whether GCC should generate code to use the optional BWX, CIX, FIX and MAX instruction sets. The default is to use the instruction sets supported by the CPU type specified via <samp><span class="option">-mcpu=</span></samp> option or that of the CPU on which GCC was built if none was specified. - <br><dt><code>-mfloat-vax</code><dt><code>-mfloat-ieee</code><dd><a name="index-mfloat_002dvax-1303"></a><a name="index-mfloat_002dieee-1304"></a>Generate code that uses (does not use) VAX F and G floating-point + <br><dt><code>-mfloat-vax</code><dt><code>-mfloat-ieee</code><dd><a name="index-mfloat_002dvax-1305"></a><a name="index-mfloat_002dieee-1306"></a>Generate code that uses (does not use) VAX F and G floating-point arithmetic instead of IEEE single and double precision. - <br><dt><code>-mexplicit-relocs</code><dt><code>-mno-explicit-relocs</code><dd><a name="index-mexplicit_002drelocs-1305"></a><a name="index-mno_002dexplicit_002drelocs-1306"></a>Older Alpha assemblers provided no way to generate symbol relocations + <br><dt><code>-mexplicit-relocs</code><dt><code>-mno-explicit-relocs</code><dd><a name="index-mexplicit_002drelocs-1307"></a><a name="index-mno_002dexplicit_002drelocs-1308"></a>Older Alpha assemblers provided no way to generate symbol relocations except via assembler macros. Use of these macros does not allow optimal instruction scheduling. GNU binutils as of version 2.12 supports a new syntax that allows the compiler to explicitly mark @@ -203,7 +203,7 @@ which relocations should apply to which instructions. This option is mostly useful for debugging, as GCC detects the capabilities of the assembler when it is built and sets the default accordingly. - <br><dt><code>-msmall-data</code><dt><code>-mlarge-data</code><dd><a name="index-msmall_002ddata-1307"></a><a name="index-mlarge_002ddata-1308"></a>When <samp><span class="option">-mexplicit-relocs</span></samp> is in effect, static data is + <br><dt><code>-msmall-data</code><dt><code>-mlarge-data</code><dd><a name="index-msmall_002ddata-1309"></a><a name="index-mlarge_002ddata-1310"></a>When <samp><span class="option">-mexplicit-relocs</span></samp> is in effect, static data is accessed via <dfn>gp-relative</dfn> relocations. When <samp><span class="option">-msmall-data</span></samp> is used, objects 8 bytes long or smaller are placed in a <dfn>small data area</dfn> (the <code>.sdata</code> and <code>.sbss</code> sections) and are accessed via @@ -219,7 +219,7 @@ heap instead of in the program's data segment. <p>When generating code for shared libraries, <samp><span class="option">-fpic</span></samp> implies <samp><span class="option">-msmall-data</span></samp> and <samp><span class="option">-fPIC</span></samp> implies <samp><span class="option">-mlarge-data</span></samp>. - <br><dt><code>-msmall-text</code><dt><code>-mlarge-text</code><dd><a name="index-msmall_002dtext-1309"></a><a name="index-mlarge_002dtext-1310"></a>When <samp><span class="option">-msmall-text</span></samp> is used, the compiler assumes that the + <br><dt><code>-msmall-text</code><dt><code>-mlarge-text</code><dd><a name="index-msmall_002dtext-1311"></a><a name="index-mlarge_002dtext-1312"></a>When <samp><span class="option">-msmall-text</span></samp> is used, the compiler assumes that the code of the entire program (or shared library) fits in 4MB, and is thus reachable with a branch instruction. When <samp><span class="option">-msmall-data</span></samp> is used, the compiler can assume that all local symbols share the @@ -228,7 +228,7 @@ required for a function call from 4 to 1. <p>The default is <samp><span class="option">-mlarge-text</span></samp>. - <br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-1311"></a>Set the instruction set and instruction scheduling parameters for + <br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-1313"></a>Set the instruction set and instruction scheduling parameters for machine type <var>cpu_type</var>. You can specify either the ‘<samp><span class="samp">EV</span></samp>’ style name or the corresponding chip number. GCC supports scheduling parameters for the EV4, EV5 and EV6 family of processors and will @@ -257,7 +257,7 @@ which selects the best architecture option for the host processor. <samp><span class="option">-mcpu=native</span></samp> has no effect if GCC does not recognize the processor. - <br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-1312"></a>Set only the instruction scheduling parameters for machine type + <br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-1314"></a>Set only the instruction scheduling parameters for machine type <var>cpu_type</var>. The instruction set is not changed. <p>Native toolchains also support the value ‘<samp><span class="samp">native</span></samp>’, @@ -265,7 +265,7 @@ which selects the best architecture option for the host processor. <samp><span class="option">-mtune=native</span></samp> has no effect if GCC does not recognize the processor. - <br><dt><code>-mmemory-latency=</code><var>time</var><dd><a name="index-mmemory_002dlatency-1313"></a>Sets the latency the scheduler should assume for typical memory + <br><dt><code>-mmemory-latency=</code><var>time</var><dd><a name="index-mmemory_002dlatency-1315"></a>Sets the latency the scheduler should assume for typical memory references as seen by the application. This number is highly dependent on the memory access patterns used by the application and the size of the external cache on the machine. |