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| author | Stephen Chu <stephen.chu@synaptics.corp-partner.google.com> | 2023-12-14 00:33:39 +0800 |
|---|---|---|
| committer | Treehugger Robot <android-test-infra-autosubmit@system.gserviceaccount.com> | 2023-12-14 02:00:59 +0000 |
| commit | fc09fbeafec0138da05512a44fb83330a5c0671e (patch) | |
| tree | 688d096fe049f743d71b5a30a56a6ccb105da7a3 | |
| parent | daa08452d9997e85995cc76fde64ae0cf71e17c4 (diff) | |
| download | dhd43752p-android-gs-bluejay-5.10-android14-qpr2.tar.gz | |
DHD: Restore clock status after CTO initandroid-u-qpr2-beta-3_r0.7android-u-qpr2-beta-3_r0.6android-u-qpr2-beta-3_r0.5android-u-qpr2-beta-3_r0.4android-u-qpr2-beta-3_r0.3android-u-qpr2-beta-3_r0.2android-u-qpr2-beta-3.1_r0.7android-u-qpr2-beta-3.1_r0.5android-u-qpr2-beta-3.1_r0.4android-u-qpr2-beta-3.1_r0.3android-u-qpr2-beta-3.1_r0.2android-u-qpr2-beta-3.1_r0.1android-14.0.0_r0.76android-14.0.0_r0.75android-14.0.0_r0.74android-14.0.0_r0.73android-14.0.0_r0.72android-14.0.0_r0.71android-14.0.0_r0.66android-14.0.0_r0.65android-14.0.0_r0.64android-14.0.0_r0.63android-14.0.0_r0.62android-14.0.0_r0.61android-14.0.0_r0.56android-14.0.0_r0.55android-14.0.0_r0.54android-14.0.0_r0.53android-14.0.0_r0.52android-14.0.0_r0.51android-gs-tangorpro-5.10-android14-qpr2-betaandroid-gs-tangorpro-5.10-android14-qpr2android-gs-raviole-5.10-android14-qpr2-betaandroid-gs-raviole-5.10-android14-qpr2android-gs-pantah-5.10-android14-qpr2-betaandroid-gs-pantah-5.10-android14-qpr2android-gs-lynx-5.10-android14-qpr2-betaandroid-gs-lynx-5.10-android14-qpr2android-gs-felix-5.10-android14-qpr2-betaandroid-gs-felix-5.10-android14-qpr2android-gs-bluejay-5.10-android14-qpr2-betaandroid-gs-bluejay-5.10-android14-qpr2
Bug: 315252799
Test: No ramdump in T6pro reboot test
Change-Id: I23ab938aa48055428e6048a2cc04b484017c4977
Signed-off-by: Stephen Chu <stephen.chu@synaptics.corp-partner.google.com>
| -rw-r--r-- | dhd_pcie.c | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -2212,6 +2212,13 @@ dhdpcie_dongle_attach(dhd_bus_t *bus) if (PCIECTO_ENAB(bus)) { dhdpcie_cto_init(bus, TRUE); } + cc = (chipcregs_t*)si_setcore(bus->sih, CC_CORE_ID, 0); + if (cc) { + AND_REG(osh, &cc->clk_ctl_st, ~CCS_FORCEHT); + } else { + DHD_ERROR(("CC is NULL\n")); + } + si_setcore(bus->sih, origidx, 0); } /* need to set the force_bt_quiesce flag here |