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/**
* \file
*
* \brief Chip-specific system clock manager configuration
*
* Copyright (C) 2011 Atmel Corporation. All rights reserved.
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED
// ===== System Clock Source Options
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_OSC0
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL0
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL1
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC120M
// ===== PLL0 Options
//#define CONFIG_PLL0_SOURCE PLL_SRC_OSC0
//#define CONFIG_PLL0_MUL 4 /* Fpll = (Fclk * PLL_mul) / PLL_div */
//#define CONFIG_PLL0_DIV 1 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== PLL1 Options
#define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
#define CONFIG_PLL1_MUL 8 /* Fpll = (Fclk * PLL_mul) / PLL_div */
#define CONFIG_PLL1_DIV 2 /* Fpll = (Fclk * PLL_mul) / PLL_div */
// ===== System Clock Bus Division Options
//#define CONFIG_SYSCLK_CPU_DIV 0 /* Fcpu = Fsys/(2 ^ CPU_div) */
//#define CONFIG_SYSCLK_PBA_DIV 0 /* Fpba = Fsys/(2 ^ PBA_div) */
//#define CONFIG_SYSCLK_PBB_DIV 0 /* Fpbb = Fsys/(2 ^ PBB_div) */
// ===== Peripheral Clock Management Options
//#define CONFIG_SYSCLK_INIT_CPUMASK ((1 << SYSCLK_SYSTIMER) | (1 << SYSCLK_OCD))
//#define CONFIG_SYSCLK_INIT_PBAMASK (1 << SYSCLK_USART0)
//#define CONFIG_SYSCLK_INIT_PBBMASK (1 << SYSCLK_HMATRIX)
//#define CONFIG_SYSCLK_INIT_HSBMASK (1 << SYSCLK_MDMA_HSB)
// ===== USB Clock Source Options
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 1 /* Fusb = Fsys/(2 ^ USB_div) */
#endif /* CONF_CLOCK_H_INCLUDED */
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