diff options
| author | Frank Barchard <fbarchard@google.com> | 2016-02-05 14:49:54 -0800 |
|---|---|---|
| committer | Frank Barchard <fbarchard@google.com> | 2016-02-05 14:49:54 -0800 |
| commit | 0d880e5bc07cde197a5a0a4e1bb4bda408373f6f (patch) | |
| tree | 76e05e47017eb9ec5600cc5e819d54fe5ef3407a /source/convert_from.cc | |
| parent | af90e82155a42ec8239685ca8626c547c7173220 (diff) | |
| download | libyuv-0d880e5bc07cde197a5a0a4e1bb4bda408373f6f.tar.gz | |
rename MIPS_DSPR2 to DSPR2 for consistency
When attempting to normalize function names to end in Row_SIMD it was made
harder with MIPS_DSPR2 naming convention.
Other CPUs do not include the vendor. This should be named consistently.
Removed the DISABLE_MIPS in favour of DISABLE_ASM for consistency with other
processors.
TBR=harryjin@google.com
BUG=libyuv:562
Review URL: https://codereview.chromium.org/1677633002 .
Diffstat (limited to 'source/convert_from.cc')
| -rw-r--r-- | source/convert_from.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/source/convert_from.cc b/source/convert_from.cc index adce5299..3bc9eb1b 100644 --- a/source/convert_from.cc +++ b/source/convert_from.cc @@ -498,13 +498,13 @@ static int I420ToRGBAMatrix(const uint8* src_y, int src_stride_y, } } #endif -#if defined(HAS_I422TORGBAROW_MIPS_DSPR2) - if (TestCpuFlag(kCpuHasMIPS_DSPR2) && IS_ALIGNED(width, 4) && +#if defined(HAS_I422TORGBAROW_DSPR2) + if (TestCpuFlag(kCpuHasDSPR2) && IS_ALIGNED(width, 4) && IS_ALIGNED(src_y, 4) && IS_ALIGNED(src_stride_y, 4) && IS_ALIGNED(src_u, 2) && IS_ALIGNED(src_stride_u, 2) && IS_ALIGNED(src_v, 2) && IS_ALIGNED(src_stride_v, 2) && IS_ALIGNED(dst_rgba, 4) && IS_ALIGNED(dst_stride_rgba, 4)) { - I422ToRGBARow = I422ToRGBARow_MIPS_DSPR2; + I422ToRGBARow = I422ToRGBARow_DSPR2; } #endif @@ -888,12 +888,12 @@ int I420ToRGB565Dither(const uint8* src_y, int src_stride_y, } } #endif -#if defined(HAS_I422TOARGBROW_MIPS_DSPR2) - if (TestCpuFlag(kCpuHasMIPS_DSPR2) && IS_ALIGNED(width, 4) && +#if defined(HAS_I422TOARGBROW_DSPR2) + if (TestCpuFlag(kCpuHasDSPR2) && IS_ALIGNED(width, 4) && IS_ALIGNED(src_y, 4) && IS_ALIGNED(src_stride_y, 4) && IS_ALIGNED(src_u, 2) && IS_ALIGNED(src_stride_u, 2) && IS_ALIGNED(src_v, 2) && IS_ALIGNED(src_stride_v, 2)) { - I422ToARGBRow = I422ToARGBRow_MIPS_DSPR2; + I422ToARGBRow = I422ToARGBRow_DSPR2; } #endif #if defined(HAS_ARGBTORGB565DITHERROW_SSE2) |