From 0c0c5f940a3fc58c84b51765fc04f0294b42fd2d Mon Sep 17 00:00:00 2001
From: Jean-Marc Valin <jean-marc.valin@usherbrooke.ca>
Date: Mon, 7 Mar 2011 20:54:33 -0500
Subject: Support for glitchles mode switching

Uses a 5ms redundant CELT frame embedded into the SILK or hybrid
packet to handle the switching. It's still possible to use the
PLC-based method when no redundant packet is included.
---
 celt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'celt/x86')

diff --git a/celt b/celt
index c79c4e3b..9bac8c17 160000
--- a/celt
+++ b/celt
@@ -1 +1 @@
-Subproject commit c79c4e3bc7270b08a2800a2dd9d9a5f02767024d
+Subproject commit 9bac8c17d57ea99192de09f8b97300b3dee0422f
-- 
cgit v1.2.3