From 43120f00758219a784f952754f33b9788a8d731b Mon Sep 17 00:00:00 2001 From: Jonathan Lennox Date: Mon, 3 Aug 2015 17:04:27 -0400 Subject: Reorganize x86 SSE intrinsics code. Enable x86 intrinsics when building in floating-point mode. Support SSE as an arch value. Use RTCD to conditionally enable existing floating-point Celt SSE code. Call functions directly (without RTCD) when their architecture can be presumed. Use SSE4.1 intrinsics optimized code for Silk even in floating-point mode. --- celt/mips/celt_mipsr1.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'celt/mips') diff --git a/celt/mips/celt_mipsr1.h b/celt/mips/celt_mipsr1.h index 03915d88..7915d596 100644 --- a/celt/mips/celt_mipsr1.h +++ b/celt/mips/celt_mipsr1.h @@ -56,7 +56,7 @@ #define OVERRIDE_comb_filter void comb_filter(opus_val32 *y, opus_val32 *x, int T0, int T1, int N, opus_val16 g0, opus_val16 g1, int tapset0, int tapset1, - const opus_val16 *window, int overlap) + const opus_val16 *window, int overlap, int arch) { int i; opus_val32 x0, x1, x2, x3, x4; -- cgit v1.2.3