Commit label r00088.2 - ES2 0.0.088.2

TRACKING-ID:db40d318-f9e4-4d1e-8ac6-41266717b2b8

9 files changed, 608 insertions, 20 deletions

diff --git a/display/blair-sde-display-qrd.dtsi b/display/blair-sde-display-qrd.dtsi
index a197818..9d188f7 100755
--- a/display/blair-sde-display-qrd.dtsi
+++ b/display/blair-sde-display-qrd.dtsi
@@ -1,5 +1,12 @@
 /* Should extend holi-sde-display-qrd-pm6125.dtsi */
 
+&dsi_panel_pwr_supply_avdd {
+	qcom,panel-supply-entry@0 {
+		qcom,supply-min-voltage = <1860000>;
+		qcom,supply-max-voltage = <1860000>;
+	};
+};
+
 &dsi_r66451_amoled_cmd {
 	/delete-property/ qcom,mdss-dsi-t-clk-post;
 	/delete-property/ qcom,mdss-dsi-t-clk-pre;
diff --git a/display/dsi-panel-ext-bridge-1080p.dtsi b/display/dsi-panel-ext-bridge-1080p.dtsi
index 07d398e..38c25ef 100755
--- a/display/dsi-panel-ext-bridge-1080p.dtsi
+++ b/display/dsi-panel-ext-bridge-1080p.dtsi
@@ -20,8 +20,8 @@
 		qcom,mdss-dsi-lane-3-state;
 		qcom,mdss-dsi-dma-trigger = "trigger_sw";
 		qcom,mdss-dsi-mdp-trigger = "none";
-		qcom,mdss-dsi-t-clk-post = <0x03>;
-		qcom,mdss-dsi-t-clk-pre = <0x24>;
+		qcom,mdss-dsi-t-clk-post = <0x0a>;
+		qcom,mdss-dsi-t-clk-pre = <0x21>;
 		qcom,mdss-dsi-force-clock-lane-hs;
 		qcom,mdss-dsi-ext-bridge-mode;
 
diff --git a/display/dsi-panel-rm69090-amoled-178-vid.dtsi b/display/dsi-panel-rm69090-amoled-178-vid.dtsi
new file mode 100755
index 0000000..3b60514
--- /dev/null
+++ b/display/dsi-panel-rm69090-amoled-178-vid.dtsi
@@ -0,0 +1,77 @@
+&mdss_mdp {
+	dsi_rm69090_amoled_vid: qcom,mdss_dsi_rm69090_amoled_178_vid {
+		qcom,mdss-dsi-panel-name =
+			"RM69090 1.78 amoled vid mode";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,mdss-dsi-panel-physical-type = "oled";
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+		qcom,mdss-dsi-underflow-color = <0xff>;
+		qcom,mdss-dsi-border-color = <0>;
+
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-lane-map = "lane_map_0123";
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-te-pin-select = <1>;
+		qcom,mdss-dsi-te-dcs-command = <1>;
+		qcom,mdss-dsi-te-check-enable;
+		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-t-clk-post = <0x09>;
+		qcom,mdss-dsi-t-clk-pre = <0x2c>;
+
+		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+		qcom,mdss-dsi-bl-min-level = <1>;
+		qcom,mdss-dsi-bl-max-level = <255>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-panel-width = <368>;
+				qcom,mdss-dsi-panel-height = <448>;
+				qcom,mdss-dsi-h-front-porch = <40>;
+				qcom,mdss-dsi-h-back-porch = <20>;
+				qcom,mdss-dsi-h-pulse-width = <4>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <8>;
+				qcom,mdss-dsi-v-front-porch = <6>;
+				qcom,mdss-dsi-v-pulse-width = <2>;
+				qcom,mdss-dsi-h-left-border = <0>;
+				qcom,mdss-dsi-h-right-border = <0>;
+				qcom,mdss-dsi-v-top-border = <0>;
+				qcom,mdss-dsi-v-bottom-border = <0>;
+
+				qcom,mdss-dsi-on-command = [
+					15 01 00 00 00 00 02 FE 01
+					15 01 00 00 00 00 02 0D 01
+					15 01 00 00 00 00 02 6A 03
+					15 01 00 00 00 00 02 FE 00
+					15 01 00 00 00 00 02 35 00
+					15 01 00 00 00 00 02 51 FF
+					39 01 00 00 00 00 05 2A 00 10 01 7F
+					39 01 00 00 00 00 05 2B 00 00 01 BF
+					05 01 00 00 78 00 02 11 00
+					05 01 00 00 40 00 02 29 00
+				];
+
+
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 14 00 02 28 00
+					05 01 00 00 78 00 02 10 00
+					15 01 00 00 00 00 02 4F 01];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};
diff --git a/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi
index 4299f95..39cf853 100755
--- a/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi
+++ b/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi
@@ -51,21 +51,27 @@
 				qcom,mdss-dsi-v-bottom-border = <0>;
 
 				qcom,mdss-dsi-on-command = [
+					15 01 00 00 00 00 02 FE 20
+					15 01 00 00 00 00 02 5A 0E
+					15 01 00 00 00 00 02 58 07
 					15 01 00 00 00 00 02 FE 00
-					15 01 00 00 00 00 02 C4 80
-					39 01 00 00 00 00 05 2A 00 06 01 61
-					39 01 00 00 00 00 05 2B 00 00 01 B9
-					39 01 00 00 00 00 05 30 00 01 01 B8
-					39 01 00 00 00 00 05 31 00 07 01 60
-					15 01 00 00 00 00 02 35 00
+					39 01 00 00 00 00 05 2A 00 00 01 3F
+					39 01 00 00 00 00 05 2B 00 00 01 67
+					39 01 00 00 00 00 05 30 00 00 01 67
+					39 01 00 00 00 00 05 31 00 00 01 3F
+					15 01 00 00 00 00 02 35 02
+					15 01 00 00 00 00 02 53 20
 					15 01 00 00 00 00 02 51 FF
-					05 01 00 00 60 00 02 11 00
+					15 01 00 00 00 00 02 63 FF
+					05 01 00 00 00 00 02 12 00
+					05 01 00 00 32 00 02 11 00
 					05 01 00 00 00 00 02 29 00
 				];
 				qcom,mdss-dsi-off-command = [
-					05 01 00 00 14 00 02 28 00
-					05 01 00 00 78 00 02 10 00
-					15 01 00 00 00 00 02 4F 01];
+					05 01 00 00 00 00 02 28 00
+					05 01 00 00 53 00 02 10 00
+					15 01 00 00 00 00 02 4F 01
+				];
 				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
 				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
 				qcom,mdss-dsi-lp2-command = [
@@ -76,8 +82,8 @@
 				qcom,mdss-dsi-nolp-command = [
 					05 01 00 00 1f 00 01 38 /* Idle-Mode Off  */
 					15 01 00 00 00 00 02 FE 00
-					39 01 00 00 00 00 05 2A 00 06 01 61
-					39 01 00 00 00 00 05 2B 00 00 01 B9
+					39 01 00 00 00 00 05 2A 00 00 01 3F
+					39 01 00 00 00 00 05 2B 00 00 01 67
 					05 01 00 00 00 00 02 12 00
 				];
 			};
diff --git a/display/monaco-sde-display.dtsi b/display/monaco-sde-display.dtsi
index 96f16f6..fe7a8fc 100755
--- a/display/monaco-sde-display.dtsi
+++ b/display/monaco-sde-display.dtsi
@@ -1,5 +1,7 @@
 #include <dt-bindings/clock/mdss-5nm-pll-clk.h>
 #include "dsi-panel-rm69090-amoled-178-cmd.dtsi"
+#include "dsi-panel-rm69090-amoled-178-vid.dtsi"
+#include "dsi-panel-rm6d030-amoled-141-cmd.dtsi"
 
 &soc {
 	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
@@ -11,8 +13,9 @@
 			qcom,supply-name = "vddio";
 			qcom,supply-min-voltage = <1800000>;
 			qcom,supply-max-voltage = <2000000>;
-			qcom,supply-enable-load = <62000>;
+			qcom,supply-enable-load = <4000>;
 			qcom,supply-disable-load = <80>;
+			qcom,supply-ulp-load = <100>;
 			qcom,supply-post-on-sleep = <20>;
 		};
 
@@ -45,8 +48,9 @@
 			qcom,supply-name = "vddio";
 			qcom,supply-min-voltage = <1800000>;
 			qcom,supply-max-voltage = <2000000>;
-			qcom,supply-enable-load = <62000>;
+			qcom,supply-enable-load = <4000>;
 			qcom,supply-disable-load = <80>;
+			qcom,supply-ulp-load = <100>;
 			qcom,supply-post-on-sleep = <20>;
 		};
 	};
@@ -60,8 +64,9 @@
 			qcom,supply-name = "vddio";
 			qcom,supply-min-voltage = <1800000>;
 			qcom,supply-max-voltage = <2000000>;
-			qcom,supply-enable-load = <62000>;
+			qcom,supply-enable-load = <4000>;
 			qcom,supply-disable-load = <80>;
+			qcom,supply-ulp-load = <100>;
 			qcom,supply-post-on-sleep = <20>;
 		};
 
@@ -75,6 +80,38 @@
 		};
 	};
 
+	dsi_panel_pwr_supply_nolab_amoled: dsi_panel_pwr_supply_nolab_amoled {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <2000000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "ibb";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <0>;
+			qcom,supply-disable-load = <0>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	display_panel_ibb: display_panel_ibb_stub {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "display_panel_ibb";
+		regulator-min-microvolt = <4600000>;
+		regulator-max-microvolt = <6000000>;
+	};
+
 	sde_dsi: qcom,dsi-display-primary {
 		compatible = "qcom,dsi-display";
 		label = "primary";
@@ -104,6 +141,7 @@
 		qcom,platform-te-gpio = <&tlmm 73 0>;
 		qcom,panel-te-source = <0>;
 		vddio-supply = <&L21A>;
+		ibb-supply = <&display_panel_ibb>;
 		qcom,mdp = <&mdss_mdp>;
 
 		qcom,dsi-default-panel =
@@ -116,6 +154,7 @@
 };
 
 &dsi_rm69090_amoled_cmd {
+	qcom,ulps-enabled;
 	qcom,mdss-dsi-t-clk-post = <0x08>;
 	qcom,mdss-dsi-t-clk-pre = <0x0B>;
 	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", /*TODO: check these*/
@@ -132,3 +171,37 @@
 	};
 };
 
+&dsi_rm69090_amoled_vid {
+	qcom,ulps-enabled;
+	qcom,mdss-dsi-t-clk-post = <0x07>;
+	qcom,mdss-dsi-t-clk-pre = <0x09>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 0E 1B 02
+				02 02 01 02 04 09 07];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_rm6d030_amoled_cmd {
+	qcom,ulps-enabled;
+	qcom,mdss-dsi-t-clk-post = <0x07>;
+	qcom,mdss-dsi-t-clk-pre = <0x0A>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0";
+
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 0A 02 02 0F 1D 02
+				02 02 02 02 04 0A 07];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
diff --git a/display/monaco-sde.dtsi b/display/monaco-sde.dtsi
index 1518a51..4603e61 100755
--- a/display/monaco-sde.dtsi
+++ b/display/monaco-sde.dtsi
@@ -40,8 +40,8 @@
 		clock-names = "gcc_bus", "throttle_clk",
 				"iface_clk", "core_clk", "vsync_clk",
 				"lut_clk";
-		clock-rate = <0 0 0 0 0 256000000 19200000 192000000>;
-		clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>;
+		clock-rate = <0 0 0 300000000 19200000 192000000>;
+		clock-max-rate = <0 0 0 400000000 19200000 400000000>;
 
 		sde-vdd-supply = <&mdss_core_gdsc>;
 
@@ -266,6 +266,7 @@
 				qcom,supply-max-voltage = <1312000>;
 				qcom,supply-enable-load = <21800>;
 				qcom,supply-disable-load = <0>;
+				qcom,supply-ulp-load = <0>;
 			};
 		};
 
@@ -321,6 +322,7 @@
 				qcom,supply-max-voltage = <904000>;
 				qcom,supply-enable-load = <37550>;
 				qcom,supply-disable-load = <0>;
+				qcom,supply-ulp-load = <0>;
 			};
 		};
 	};
diff --git a/display/qrb2210-rb1-sde-display.dtsi b/display/qrb2210-rb1-sde-display.dtsi
new file mode 100755
index 0000000..8d03ecf
--- /dev/null
+++ b/display/qrb2210-rb1-sde-display.dtsi
@@ -0,0 +1,101 @@
+#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
+#include "dsi-panel-ext-bridge-1080p.dtsi"
+
+&soc {
+	dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <2000000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "lab";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <100000>;
+			qcom,supply-disable-load = <100>;
+		};
+
+		qcom,panel-supply-entry@2 {
+			reg = <2>;
+			qcom,supply-name = "ibb";
+			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-max-voltage = <6000000>;
+			qcom,supply-enable-load = <100000>;
+			qcom,supply-disable-load = <100>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <2000000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <2000000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+
+		qcom,panel-supply-entry@1 {
+			reg = <1>;
+			qcom,supply-name = "vdda-3p3";
+			qcom,supply-min-voltage = <3000000>;
+			qcom,supply-max-voltage = <3000000>;
+			qcom,supply-enable-load = <13200>;
+			qcom,supply-disable-load = <80>;
+		};
+	};
+
+	sde_dsi: qcom,dsi-display-primary {
+		compatible = "qcom,dsi-display";
+		label = "primary";
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+
+		clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>,
+			 <&mdss_dsi_phy0 PIX0_MUX_CLK>,
+			 <&mdss_dsi_phy0 BYTE0_SRC_CLK>,
+			 <&mdss_dsi_phy0 PIX0_SRC_CLK>,
+			 <&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>,
+			 <&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>;
+		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+			"src_byte_clk0", "src_pixel_clk0",
+			"shadow_byte_clk0", "shadow_pixel_clk0";
+
+		vddio-supply = <&L15A>;
+		qcom,mdp = <&mdss_mdp>;
+	};
+};
+
+&mdss_mdp {
+	  connectors = <&smmu_sde_unsec &sde_dsi>;
+};
diff --git a/display/qrb2210-rb1-sde.dtsi b/display/qrb2210-rb1-sde.dtsi
new file mode 100755
index 0000000..b37deff
--- /dev/null
+++ b/display/qrb2210-rb1-sde.dtsi
@@ -0,0 +1,322 @@
+#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
+
+&soc {
+
+	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+		compatible = "qcom,smmu_sde_unsec";
+		iommus = <&apps_smmu 0x420 0x2>;
+		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		qcom,iommu-faults = "non-fatal";
+		qcom,iommu-earlymap; /* for cont-splash */
+	};
+
+	smmu_sde_sec: qcom,smmu_sde_sec_cb {
+		compatible = "qcom,smmu_sde_sec";
+		iommus = <&apps_smmu 0x421 0x0>;
+		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+		qcom,iommu-faults = "non-fatal";
+		qcom,iommu-vmid = <0xa>;
+	};
+
+	mdss_mdp: qcom,mdss_mdp {
+		compatible = "qcom,sde-kms";
+		reg = <0x5e00000 0x8f030>,
+		      <0x5eb0000 0x2008>,
+		      <0x5e8f000 0x02c>,
+		      <0xc125ba4 0x20>;
+		reg-names = "mdp_phys",
+			   "vbif_phys",
+			   "sid_phys",
+			   "sde_imem_phys";
+
+		clocks =
+			<&gcc GCC_DISP_AHB_CLK>,
+			<&gcc GCC_DISP_HF_AXI_CLK>,
+			<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
+			<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_AHB_CLK>,
+			<&dispcc DISP_CC_MDSS_MDP_CLK>,
+			<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
+		clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
+				 "div_clk",
+				"iface_clk", "core_clk", "vsync_clk",
+				"lut_clk";
+		clock-rate = <0 0 0 0 0 256000000 19200000 192000000>;
+		clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>;
+
+		sde-vdd-supply = <&mdss_core_gdsc>;
+
+		/* data and reg bus scale settings */
+		interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
+				<&bimc MASTER_AMPSS_M0
+				&config_noc SLAVE_DISPLAY_CFG>;
+		interconnect-names = "qcom,sde-data-bus0",
+					"qcom,sde-reg-bus";
+
+		/* interrupt config */
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		#power-domain-cells = <0>;
+
+		/* hw blocks */
+		qcom,sde-off = <0x1000>;
+		qcom,sde-len = <0x494>;
+
+		qcom,sde-ctl-off = <0x2000>;
+		qcom,sde-ctl-size = <0x1dc>;
+		qcom,sde-ctl-display-pref = "primary";
+
+		qcom,sde-mixer-off = <0x45000>;
+		qcom,sde-mixer-size = <0x320>;
+		qcom,sde-mixer-display-pref = "primary";
+
+		qcom,sde-dspp-top-off = <0x1300>;
+		qcom,sde-dspp-top-size = <0x80>;
+		qcom,sde-dspp-off = <0x55000>;
+		qcom,sde-dspp-size = <0xfe4>;
+
+		qcom,sde-intf-off = <0x0 0x6b800>;
+		qcom,sde-intf-size = <0x2b8>;
+		qcom,sde-intf-type = "none", "dsi";
+
+		qcom,sde-pp-off = <0x71000>;
+		qcom,sde-pp-size = <0xd4>;
+
+		qcom,sde-dither-off = <0x30e0>;
+		qcom,sde-dither-version = <0x00010000>;
+		qcom,sde-dither-size = <0x20>;
+
+		qcom,sde-sspp-type = "vig", "dma";
+
+		qcom,sde-sspp-off = <0x5000 0x25000>;
+		qcom,sde-sspp-src-size = <0x1f8>;
+
+		qcom,sde-sspp-xin-id = <0 1>;
+		qcom,sde-sspp-excl-rect = <1 1>;
+		qcom,sde-sspp-smart-dma-priority = <2 1>;
+		qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+		qcom,sde-mixer-pair-mask = <0>;
+
+		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+						0xb0 0xc8 0xe0 0xf8 0x110>;
+
+		qcom,sde-mixer-stage-base-layer;
+
+		qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>;
+
+		qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+		qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>;
+		qcom,sde-mixer-linewidth = <2048>;
+		qcom,sde-mixer-blendstages = <0x4>;
+		qcom,sde-panic-per-pipe;
+		qcom,sde-has-cdp;
+
+		qcom,sde-has-dim-layer;
+		qcom,sde-has-idle-pc;
+
+		qcom,sde-max-bw-low-kbps = <2700000>;
+		qcom,sde-max-bw-high-kbps = <2700000>;
+		qcom,sde-min-core-ib-kbps = <1300000>;
+		qcom,sde-min-llcc-ib-kbps = <0>;
+		qcom,sde-min-dram-ib-kbps = <1600000>;
+		qcom,sde-dram-channels = <2>;
+		qcom,sde-num-nrt-paths = <0>;
+
+		qcom,sde-vbif-off = <0>;
+		qcom,sde-vbif-size = <0x2008>;
+		qcom,sde-vbif-id = <0>;
+		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+
+		/*Pending macrotile & macrotile-qseed has the same configs */
+
+		qcom,sde-danger-lut = <0x000000ff 0x00000000
+			0x00000000 0x00000000 0x00000000>;
+
+		qcom,sde-safe-lut-linear = <0 0xfff0>;
+
+		qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+
+		qcom,sde-cdp-setting = <1 0>;
+
+		qcom,sde-qos-cpu-mask = <0x3>;
+		qcom,sde-qos-cpu-dma-latency = <300>;
+
+		qcom,sde-secure-sid-mask = <0x0000421>;
+		qcom,sde-num-mnoc-ports = <1>;
+		qcom,sde-axi-bus-width = <16>;
+
+		qcom,sde-reg-bus,vectors-KBps = <0 0>,
+				<0 76800>,
+				<0 150000>,
+				<0 300000>;
+
+		qcom,sde-sspp-vig-blocks {
+		};
+
+		qcom,sde-dspp-blocks {
+			qcom,sde-dspp-igc = <0x0 0x00030001>;
+			qcom,sde-dspp-hsic = <0x800 0x00010007>;
+			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+			qcom,sde-dspp-hist = <0x800 0x00010007>;
+			qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+			qcom,sde-dspp-dither = <0x82c 0x00010007>;
+		};
+
+		qcom,platform-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,platform-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "sde-vdd";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		/* data and reg bus scale settings */
+		qcom,sde-data-bus {
+			qcom,msm-bus,name = "mdss_sde";
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+				<22 512 0 0>,
+				<22 512 0 4800000>,
+				<22 512 0 4800000>;
+		};
+
+		qcom,sde-limits {
+			qcom,sde-linewidth-limits {
+				qcom,sde-limit-name = "sspp_linewidth_usecases";
+				qcom,sde-limit-cases = "vig", "dma";
+				qcom,sde-limit-ids= <0x1 0x2>;
+				qcom,sde-limit-values = <0x1 2160>,
+							<0x2 2160>;
+			};
+
+			qcom,sde-bw-limits {
+				qcom,sde-limit-name = "sde_bwlimit_usecases";
+				qcom,sde-limit-cases = "per_vig_pipe",
+							"per_dma_pipe",
+							"total_max_bw",
+							"camera_concurrency";
+				qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
+				qcom,sde-limit-values = <0x1 2700000>,
+							<0x9 2700000>,
+							<0x2 2700000>,
+							<0xa 2700000>,
+							<0x4 2700000>,
+							<0xc 2700000>;
+			};
+		};
+	};
+
+	mdss_dsi0: qcom,mdss_dsi0_ctrl {
+		compatible = "qcom,dsi-ctrl-hw-v2.4";
+		label = "dsi-ctrl-0";
+		cell-index = <0>;
+		reg = <0x5e94000 0x400>,
+			<0x5f08000 0x4>;
+		reg-names = "dsi_ctrl", "disp_cc_base";
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <4 0>;
+		vdda-1p2-supply = <&L5A>;
+		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+			<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_ESC0_CLK>;
+		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+				"pixel_clk", "pixel_clk_rcg", "esc_clk";
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-1p2";
+				qcom,supply-min-voltage = <1232000>;
+				qcom,supply-max-voltage = <1312000>;
+				qcom,supply-enable-load = <21800>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "refgen";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
+		compatible = "qcom,dsi-phy-v2.0";
+		label = "dsi-phy-0";
+		cell-index = <0>;
+		#clock-cells = <1>;
+		reg = <0x5e94400 0x588>,
+			<0x5e01400 0x100>,
+			<0x5e94200 0x100>,
+			<0x5e94400 0x588>,
+			<0x5f03000 0x8>;
+		reg-names = "dsi_phy", "phy_clamp_base",
+			"dyn_refresh_base", "pll_base", "gdsc_base";
+		pll-label = "dsi_pll_14nm";
+		memory-region = <&dfps_data_memory>;
+		vdda-0p9-supply = <&VDD_MX_LEVEL>;
+		qcom,platform-strength-ctrl = [ff 06
+						ff 06
+						ff 06
+						ff 06
+						ff 00];
+		qcom,platform-lane-config = [00 00 10 0f
+						00 00 10 0f
+						00 00 10 0f
+						00 00 10 0f
+						00 00 10 8f];
+		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+		qcom,panel-allow-phy-poweroff;
+		qcom,dsi-pll-ssc-en;
+		qcom,dsi-pll-ssc-mode = "down-spread";
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-0p9";
+				qcom,supply-min-voltage =
+					<RPM_SMD_REGULATOR_LEVEL_NOM>;
+				qcom,supply-max-voltage =
+					<RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
+				qcom,supply-off-min-voltage =
+					<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+};
diff --git a/display/sdxlemur-qpic-display.dtsi b/display/sdxlemur-qpic-display.dtsi
index b6ede6f..393b344 100755
--- a/display/sdxlemur-qpic-display.dtsi
+++ b/display/sdxlemur-qpic-display.dtsi
@@ -5,7 +5,7 @@
 		reg = <0x1b00000 0x24000>;
 		reg-names = "qpic_base";
 
-		interrupts = <0 75 0>;
+		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "qpic_irq";
 
 		interconnect-names = "qpic-display-data-bus";